SAN FRANCISCO, Dec. 10, 2024 – At the 2024 IEEE International Electron Devices Meeting (IEDM), Intel’s Foundry Division presented four major technological breakthroughs in advanced process engineering to the global semiconductor industry. Covering a wide range of cutting-edge areas such as new materials, heterogeneous packaging, transistor miniaturization and power devices, these technological innovations exemplify Intel’s leadership in advancing semiconductor technology. These breakthrough technologies not only lay the foundation for Intel’s next-generation product performance enhancement, but also provide key support for achieving the ambitious goal of integrating 1 trillion transistors on a single chip by 2030.
As part of Intel’s “5 Process Nodes in 4 Years” initiative, these technologies will help Intel push the performance boundaries of future process nodes and continue to advance Moore’s Law, a strategic goal that will not only help improve the performance of data centers, AI processing, mobile devices, as well as 5G and next-generation communications technologies, but also provide the foundation for high-performance, high-performance, high-performance products. communications technologies, but also fuels technological advances in areas such as high-performance computing and quantum computing.
Ruthenium interconnect technology: solving the micronization bottleneck, improving performance and energy efficiency
At the IEDM, Intel debuted its Ruthenium Reduction Method (RRM) ruthenium interconnect technology, a technological breakthrough in the field of chip interconnects by replacing traditional copper materials with ruthenium metal and incorporating air gaps. The low resistivity of ruthenium and the introduction of air gaps enable a significant reduction in inter-chip capacitance of up to 25%. This technology is particularly suitable for process nodes with chip interconnect line pitches of less than or equal to 25 nanometers, and is able to maintain low capacitance and high signal transmission efficiency during the micro-miniaturization process, thus reducing power consumption, lowering latency, and improving overall performance.
Ruthenium interconnect technology has significant advantages over traditional copper inlay processes. It not only significantly reduces energy loss in the interconnect process while maintaining high performance, but also improves production efficiency and reduces material costs, making it more feasible and cost-effective for mass production. As process nodes continue to shrink, ruthenium interconnect technology will play an important role in Intel’s future foundry processes, becoming the key to advancing the development of advanced chip technology and improving integration.
Selective Layer Transfer (SLT) technology: 100X throughput improvement for ultra-high density integration
The second technology demonstrated was Intel’s innovative breakthrough in heterogeneous integration – Selective Layer Transfer (SLT) technology, which enables ultra-thin die to be integrated in a more flexible and efficient manner through a revolutionary layer transfer process. Compared to traditional chip-to-wafer bonding technology, SLT not only significantly reduces chip size, but also enables higher aspect ratios and functional densities in a single package. This enables Intel to integrate more chips into a smaller space, thereby improving the performance and integration of the entire system.
One of the highlights of SLT technology is a throughput increase of up to 100 times. This means that in the chip manufacturing process, SLT technology can dramatically accelerate the speed of inter-chip packaging, significantly improving production efficiency. This technological breakthrough opens up the possibility of efficient manufacturing of future Very Large Scale Integrated Circuits (VLSI), while providing a solution to meet the growing demand for chip performance and integration in application areas such as AI, 5G, and IoT.
SLT technology also supports multi wafer die integration, through hybrid bonding or fusion bonding technology, able to integrate multiple dies from different wafers in one package. This not only improves the functional density of the chip package, but also enhances the ability of different functional modules to work together, providing technical support for the development of multi-core processors, heterogeneous computing platforms and integrated circuits.
Silicon RibbonFET CMOS transistors: driving the continued evolution of moore’s law
In the semiconductor transistor space, Intel demonstrated the latest results of its silicon-based RibbonFET CMOS transistor technology. This technology represents a significant advancement in transistor miniaturization by Intel, employing a gate length of 6 nanometers and dramatically reducing channel thickness. This innovation not only allows the transistor to shrink further in size, but also effectively suppresses the short-channel effect, improving switching speed and performance.
RibbonFET technology offers significant advantages over conventional FinFETs (finned field effect transistors). It significantly reduces leakage current and power consumption by increasing gate-to-channel control, while achieving industry-leading performance. With the further miniaturization of the transistor, the RibbonFET will provide even more computing power for next-generation high-performance computing, AI training and reasoning, and big data processing.
What’s more, the silicon-based RibbonFET CMOS transistor technology provides key support for continuing to advance Moore’s Law. By shrinking the gate length and reducing the channel thickness of the transistors, Intel is able to achieve higher transistor densities on smaller process nodes, thereby increasing the computing power of the chip without increasing power consumption. This technological advancement will directly contribute to the continuation of Moore’s Law over the next decade, supporting the long-term development of the global semiconductor industry.
2D GAA transistor technology: a new chapter in transistor miniaturization
Intel has also made significant advances in its full-surround gate (GAA) technology. Focusing on the gate oxide module of the 2D GAA transistor, Intel has successfully shrunk the gate length to 30 nm, significantly improving the transistor’s performance and power efficiency. GAA technology provides stronger gate control and effective suppression of the short-channel effect through the use of a full-surrounded gate structure, which further facilitates the miniaturization of the transistor and the improvement of its performance.
Intel’s research team also made a breakthrough in 2D transition metal disulfide (TMD) materials, which have excellent electrical properties and are expected to replace traditional silicon materials in the future, driving further development of next-generation transistor processes. With the introduction of 2D materials, Intel has not only made significant progress in transistor miniaturization, but also paved the way for the next round of technological revolution in the semiconductor field.
This technological advancement opens up the possibility of realizing high-performance transistors at smaller nodes in the future, especially in ultra-high-performance computing, low-power devices and smart hardware, and GAA technology is expected to be at the heart of future process technology, driving new computing architectures and chip design concepts.
GaN technology: enhancing the performance of power devices to support the future demands of electronic devices
In the field of power devices, Intel also demonstrated its significant progress in gallium nitride (GaN) technology. By realizing the fabrication of miniaturized and enhanced GaN MOSHEMTs on 300mm GaN-on-TRSOI (Trap-Rich Silicon on Insulator) substrates, Intel demonstrated its cutting-edge research in the field of high-performance power devices. This innovative technology significantly reduces signal loss and improves signal linearity, thus optimizing the efficiency of power electronic devices, which are particularly suitable for high power applications such as high-speed power conversion, communications and electric vehicles.
The advantages of GaN material in high frequency, high power and high efficiency conversion make it has a wide range of potential applications in future 5G communications, data centers, and electric vehicle charging.Intel’s continuous innovation in this field not only provides new opportunities for the diversified layout of its own chip business, but also provides technological support for the global electronics industry‘s green transformation and energy efficiency improvement.
Conclusion
Intel’s four major technology breakthroughs at IEDM 2024 demonstrate the company’s deep strength and leadership in semiconductor technology. Whether it’s innovations in transistor miniaturization, heterogeneous integration, interconnect technology or power electronics, Intel continues to push the industry toward higher technological goals. These technological innovations not only give Intel an edge in the future of semiconductor competition, but also provide key support for advancing the industry as a whole and perpetuating Moore’s Law. As these technologies mature and become commercially available, Intel will continue to lead the global semiconductor industry and provide strong support for the future digital economy, smart society and technological advancement.
