As Moore's Law continues to advance, transistors are getting smaller and denser, with more layers in the stack. At this point, the details become more capable of squeezing more performance out of a chip, and backside power is one. At the same time, it may also be the key to achieving 1nm. Throughout the current industry, Intel pre-emptive, TSMC, Samsung plus follow up, in the IEDM2023, Intel continues to promote this technology, this time Intel has released the back contact such as "king bomb" new technology, at the same time will be 3D stacking and PowerVia and back contact three technologies combined, proving that this technology may eventually be in the crystal. The combination of 3D stacking with PowerVia and backside contacts proves that this technology could eventually play a role in transistor density miniaturization.
Why Back Side Power Supply
Backside power supply (BSP/BS-PDN) is the process of relocating the power supply network, which was originally laid out with the transistor, directly to the back of the transistor and rearranging it. To understand the value of the BSP network, you need to start with chip manufacturing.
The power transfer network inside the chip starts with etching the first layer of the transistor, which is the smallest and most complex layer on the chip, and where high-precision tools such as EUV and multi-exposure are most needed. In short, it is the most expensive and complex layer on the chip and has a major impact on how the chip is constructed and how it is tested.
On top of this, various metal layers are gradually built to route all the wiring needed to transfer electrons between the different transistors (including caches, buffers, and accelerators), and further to route power to higher layers, much like making a pizza. Modern high-performance processors typically have 10 to 20 metal layers. On top of that, there are two other “giant metal” layers, which are used only for power cabling and to house external interfaces.
Once the chip is manufactured, it is turned upside down and flipped into a flip-flop, so that all the connections, including the power and data interfaces, go to the bottom of the chip, and the transistors are on the top of the chip. The advantage of flip-flops is that chip debugging and cooling can be accessed from the top, thus becoming easier.
However, the disadvantage of front-end powering is that both the power and signal wires are located on the same side of the chip. Both wires have to travel more than 15 layers down to reach the transistors, competing for space while avoiding interference, and the longer the distance, the higher the resistance and the lower the efficiency, known as the IR Drop/Droop effect. That being the case, it’s good to put it on the backside.
On the one hand, it is possible to use both the large cross-section, and low-resistance lines for the back interconnect lines, while the front side is mainly used for signal transmission, and optimize them separately and independently; on the other hand, it is possible to bring about a performance improvement by moving the power supply lines from the front to the back side, so that the originally congested front part now frees up more space; in addition, the wires are separated, which is important for reducing the process, complexity and cost.
In fact, in the past, this was not a big problem. However, as chip sizes have become smaller and smaller, this problem has become more and more apparent. There are no obvious hard limits to front-end power transfer, but given that each generation of chips is getting harder and harder to shrink, the problem has become too big, or more precisely too expensive to solve. The back power supply is to separate the signal and the power transmission network, one side is the signal, and the other side (back) is the power supply. Of course, the back power supply is not simply reversed but has many problems, including testing problems and manufacturing problems.
PowerVia: Intel’s Answer Book
According to previous information, Intel‘s backside power supply technology, called PowerVia, will be available on Intel’s 20A process node in the first half of 2024. As a key technology to continue Moore’s Law, Intel has separated the development of PowerVia technology and RibbonFET transistors to ensure that PowerVia can be properly used in the production of Intel 20A and Intel 18A process chips. The combination of PowerVia and RibbonFETs, and in particular PowerVia, is considered by Intel to be the new “Power of the Future”. The combination of PowerVia and RibbonFETs, and especially PowerVia, is seen by Intel as the new “FinFET” moment, and PowerVia is ahead of the curve, with TSMC not expected to deploy the technology until the N2P node at the end of 2026 or the beginning of 2027.
More than that, PowerVia has been compared by Intel to innovations such as strained silicon, Hi-K metal gate, and FinFET transistors, all of which Intel pioneered in the industry. “This is Intel’s initiative to usher in the angstrom era,” and more importantly, the Intel 20A and Intel 18A processes are not just for Intel products, but also have far-reaching implications for Intel Foundry Services (IFS).
Firstly, the backside power supply has a significant impact on simplifying the construction of the chip. The ability to relax the thickness of the metal layer – for example, the Intel 4 + PowerVia test node allows for a 36 nm pitch, as opposed to the 30 nm pitch required on the Intel 4 – directly simplifies the most complex and costly processing step of the entire chip, bringing it closer to the process size of the Intel 7.
Secondly, the backside power supply network also provides some of the performance improvements to the chip. Shortening the power transfer path to the transistors more directly helps to counteract the IR Droop effect, resulting in better power transfer to the transistor layer and eliminating interference, solving a decades-old interconnect bottleneck.
By the numbers, with PowerVia, the IR drop can be reduced by 30% and Fmax can be increased by 6%. This means that for engineers it is a definite plus that EM, IR power supply, and other issues will be greatly reduced, and also that cell utilization can be greatly increased to 90%, helping to achieve significant transistor miniaturization and enabling chip design companies to improve product performance and energy efficiency.
Back Side Contacts: More Possibilities for Back Side Power Delivery
At IEDM 2023, Intel will present a paper entitled Process Innovations for Future Technology Nodes with Back Side Power Delivery and 3D Device Stacking. Stacking”, a paper that provides a detailed explanation of a series of back-side power delivery innovations beyond PowerVia.
The research focuses on back-side contacts, a new technology that allows Intel, for the first time, to have a single device layer that can be connected to a transistor from above or below, or both, when needed. It can be deployed with PowerVia or on its own. That means more possibilities for backside power technology development.
What does the backside contact do? Firstly, power can be supplied directly to the transistor from the back side, via a large cross-section wire, without having to make a detour, which greatly improves performance in terms of power supply. Secondly, because there is no PowerVia, the amount of metal in the cell is reduced, and with it the capacitance and capacitive spin, resulting in faster switching and at the same time lower power consumption. Thirdly, not needing to reserve space for PowerVia allows everything to be held more tightly within the same area, meaning that more transistors can be put in per unit area. To summarise, backside contacts not only retain all the benefits of backside power technology, they also bring additional performance or energy efficiency ratio benefits and help to further enable micro area reduction.
Backside contact technology can bring about a change in the interconnect requirements for transistor stacks. Previously, most interconnects were created for single-layer transistor requirements, but when it came to starting to stack transistors, the key idea was to increase the number of transistors per unit area by stacking NMOS transistors on top of PMOS transistors. Stacked transistors create a very interesting topology for interconnects, where power and signals need to be supplied to both the top and bottom transistors at the same time, and there is no option to supply power to just one of them.
This can be achieved by using PowerVia and backside contacts, which when used in tandem allow for very efficient transistor stacking. In addition to these two key technologies, connections between the gates and between the sources of a pair of NMOS and PMOS stacks require new vertical interconnections called Gate Connections and Epi-Epi Connections, which Intel has been able to fabricate. In other words, Intel’s new vertical interconnection technology has begun to be equipped. Intel will continue to micro interconnect sizes, so Intel needs to ensure that all of the above features are consistent in smaller sizes, make them in smaller sizes, and connect them.
In terms of thermal effects, PowerVia has demonstrated that backside-powered thermal performance and response is essentially the same as a standard design without backside power at the same power density. Notably, the study found that the use of back-side contacts does not affect thermal performance. In this research, Intel has found ways to further expand on PowerVia’s backside power technology and enable transistor miniaturization. These technologies are compatible with transistor stacking, which is critical to achieving transistor stacking with high area efficiency in practice.
3D Stacking and Backside Power Running in Both Directions
At IEDM 2023, Intel also presented a paper entitled Demonstration of a Stacked CMOS Inverter at 60nm Gate Pitch with Power Via and Direct Backside Contacts. Direct Backside Device Contacts) paper that goes beyond the RibbonFET to further advance transistor miniaturization.
Simply put, this paper is a combination of the 3D stacking technology presented at IEDM 2021 with PowerVia and Backside Contacts, focusing on achieving a synergistic effect that combines device stacking with an efficient way of interconnecting devices through the use of backside powering techniques.
Recalling the early research on CMOS transistor 3D stacking presented by Intel at IEDM 2021, at the time Intel could only use front-side processing techniques, which meant that additional contacts had to be elicited, such as labelled Vcc contacts away from the transistor gates, thus taking up extra area, which would diminish the advantages offered by transistor stacking. At the time, transmission electron microscope (TEM) images showed a very thin gate, located about two-thirds of the way down the left side, which needed to independently touch the large contacts of the top and bottom transistors.
At IEDM2023, Intel successfully combined monolithic NMOS and PMOS with PowerVia and back-side contacts, demonstrating that this approach to compact, high-density device stacking is a technology that may eventually play a role in the miniaturization of transistor density. Specifically, two sets of RibbonFETs are stacked together, PMOS on the bottom and NMOS on the top, each with three Ribbons to maximize device drive current.
In traditional technology, the devices are side-by-side, and patterning (vertically patterned) is straightforward, but when the transistors are stacked, they must be patterned vertically. Although difficult, Intel can achieve vertical patterning by depositing the source and drain for the PEPI on the bottom device, which is usually made of silicon germanium, and the NEPI on the top, which is usually made of silicon.
The same operation needs to be performed on the gate portion of the device, and again the metal must be deposited vertically. It is also necessary to provide back-side contacts to individually touch the bottom device, as there is no other space that can be touched, as well as PowerVia back-side power supplies to connect the top transistor to the back of the wafer.
The wrap-around contact technology is a contact that wraps the two transistor sources together at an internal node of the inverter, or other need, which allows the same track to contact both the NEPI and the PEPI, which again provides an efficient method compared to using PowerVia and backside contact connections for some kind of wrap-around.
It’s also worth noting that, very unlike in conventional technologies where two transistors (NMOS and PMOS) have to be placed side-by-side, Intel can stack complementary field effect transistors (CFETs) vertically at gate spacings as minuscule as 60nm. At the same time, in terms of voltage transfer curves, the three technologies stacked have the same curves as an inverter (a CMOS consisting of only one NMOS and one PMOS) in RibbonFET or FinFET technology.
Next year, PowerVia will be production-ready and the first in the industry to be backside-powered, and Intel is working on ways to miniaturize the technology so that it can boost performance. At the same time, Intel is aggressively pursuing its ‘five process nodes in four years’ program and is committed to achieving one trillion transistors in a single package by 2030, and PowerVia is a major milestone for both of these goals, showing that a new and exciting era of interconnects is on the horizon.